This invention relates to semiconductor processing and more particularly to a semiconductor process that can produce bipolar and field effect transistors on the same chip.
Several BICMOS processes have been disclosed in the prior art which can result in a combination of bipolar and field effect transistors on the same semiconductor device. Examples of these prior art processes can be found in U.S. Pat. No. 4,536,945 issued Aug. 27, 1985 to G. Bruce et al. and U.S. Pat. No. 4,484,388 issued Nov. 27, 1984 to I. Hiroshi. Both of these prior art processes have been found to be limited in producing very high-speed semiconductor devices. In both of the processes the gate structure itself is used as an alignment mechanism in determining the position of the contacts that are made to the active elements of the device. In both processes the metallic contacts are made directly to the source and drain regions. The dimension of these regions is dependent upon the precision with which a hole can be placed with respect to the gate structure. This fact causes the source and drain regions to be larger than desirable, thereby causing these regions to have a larger parasitic capacitance than desirable which in turn limits high-speed operation.
In addition, the p-region that is established in these processes for the PMOS device is created by implanting boron directly into the semiconductor material. As is well-known in the art, the boron cannot be doped too heavily since it tends to channel quite readily through the crystalline structure of the semiconductor material during implantation thereby causing a larger junction depth than desired. On the other hand, a light doping of boron produces an element of the semiconductor device which has a higher resistance than desirable.